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Alternative Makefile to show Makefile facilities
Putting it all together example from a Well House Consultants training course
More on Putting it all together [link]

This example is described in the following article(s):
   • Make and makefiles - a commented example to help you learn - [link]

Source code: Make_mark_2 Module: C239

# Using a variable as a macro to save re-typing
HEADERS=Film.h HireFilm.h
HEADERS+=Expense.h iostream

# Tell Make where to look for dependencies
# in addition to current directory
VPATH=/usr/include/c++/4.1.0

# If you call up a ".txt" dependency it will be
# in your "docs" sibling directory
vpath %.txt ../docs

# Use variables for common utilities that may change
# globally and you don't want to have to rework the
# whole make file!!
CC=g++

# Global flags for all compiles
CFLAGS=-O2

# Code that calls in other code
HIGHSOURCE=Filmtest.cpp HireFilm.cpp
LOWSOURCE=Film.cpp Expense.cpp
# We want an equivalent list of object files
HIGHOBJ=$(HIGHSOURCE:%.cpp=%.o)
LOWOBJ=$(LOWSOURCE:%.cpp=%.o)

# ---------------------------------------------

# Standard Rules

# If I say "make summat.html" it copies the .txt
# file from the docs area.

# Note - first line scraps any old standard rules!

.SUFFIXES:
.SUFFIXES: .html .txt

# How to convert a .txt file into a .html one!

.txt.html:
        @echo "<html><body>" > $@
        @cat ../docs/$< >> $@
        @echo "</body></html>" >> $@
        @echo "Web Page $@ created"

# ---------------------------------------------

# First rule is what is done if you just say "make"

all: Filmtest
        @echo "The whole caboodle is now up to date"

Filmtest: $(HIGHOBJ) $(LOWOBJ) about.txt
        $(CC) -o Filmtest $(HIGHOBJ) $(LOWOBJ)

Filmtest.o: Filmtest.cpp $(HEADERS)
        $(CC) -c $(CFLAGS) Filmtest.cpp

# I want the following structure to be default
#
# Film.o: Film.cpp Film.h
# $(CC) -c $(CFLAGS) Film.cpp
#
# Expense.o: Expense.cpp Expense.h
# $(CC) -c $(CFLAGS) Expense.cpp
#
# $@ is the target
# $< is the first dependency
#
# Works for Film.cpp and Expense.cpp in this example
#

%.o: %.cpp %.h
        $(CC) -c $(CFLAGS) -o $@ $<

# Here is one we have left in because it's not
# exactly the same compile structure!

HireFilm.o: HireFilm.cpp $(HEADERS)
        $(CC) -c $(CFLAGS) HireFilm.cpp

# @ supresses command echo
# - says "carry on even if error"

clean:
        @-rm *.o
        @-rm Filmtest
        @-rm *.html
        @echo "Clean dup"

# N.B. Makefile can contain ifs and elses ...
# not shown in this particular example.
Learn about this subject
This module and example are covered on the following public courses:
 * Learning to program in C and C++
 * C++ for C Programmers
 * C and C++ Programming
 * Learning to program in C and C++
 * C and C++ Programming
Also available on on site courses for larger groups

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Other Examples
This example comes from our "Putting it all together" training module. You'll find a description of the topic and some other closely related examples on the "Putting it all together" module index page.

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