Hi
I have a text file  as shown below:
"Stage":"Switches":"Category":"Testcase":"Options":"Unique Name":"Run Number":"Comments"
"do_setup":"-tpl -flow -overwrite MSV MMMC MSV+MMMC":"script_basic":"A":"-tpl -overwrite":"tpl":"RUN_do_setup_tpl":"Create design_setup.txt"
"do_setup"::"script_basic":"A":"-flow fe -overwrite":"fe":"RUN_do_setup_fe":"Check .tcl, .conf files."
"do_lec"::"script_basic":"A":"-stage postapr -overwrite -g_ver $verilogFile -top $topModuleName":"postapr":"RUN_do_lec_postapr":"Post apr"
"do_lec"::"script_basic":"A":"-c_ver $verilogFileC -overwrite -g_ver $verilogFile -top $topModuleName -bbox $blackBox -do":"c_ver":"RUN_do_lec_c_ver":"Do file only"
"do_uniq":"-ver -top":"script_basic":"A":"-ver $verilogFile -top $topModuleName"::"RUN_do_uniq_":
"do_abstract":"-fe -se -pdk -tech -layer -gds -cell -ver -type -unit -blockage -gui -tcl -overwrite -nobackup":"script_basic":"A":"-fe -gds $gdsFile -cell $cellName -ver $verilogFile -unit 2000 -type detail -blockage place -overwrite -nobackup":"detail_place":"RUN_do_abstract_detail_place":"FE, detail, place"
"do_abstract"::"script_basic":"A":"-fe -gds $gdsFile -cell $cellName -ver $verilogFile -unit 2000 -type cover -blockage route -overwrite -nobackup":"cover_route":"RUN_do_abstract_cover_route":"FE, cover, route"
"do_abstract"::"script_basic":"A":"-fe -gds $gdsFile -cell $cellName -ver $verilogFile -unit 2000 -type cover -blockage both -tcl -overwrite -nobackup":"both_tcl":"RUN_do_abstract_both_tcl":"FE, cover, both, tcl"
"do_streamout":"-def -ver -map -unit -mode -abs -tcl -overwrite -nobackup -local -ver -map":"script_basic":"A":"-def $defFile -ver $verilogFile -unit 2000 -mode all -overwrite -nobackup -local":"all":"RUN_do_streamout_all":"Mode all."
"do_streamout"::"script_basic":"A":"-def $defFile -ver $verilogFile -unit 2000 -mode fillonly -abs -overwrite -nobackup -local":"fillonly_abs":"RUN_do_streamout_fillonly_abs":"Mode fillonly, output LEF abs."
"do_streamout"::"script_basic":"A":"-def $defFile -ver $verilogFile -unit 2000 -mode nofill -tcl -overwrite -nobackup -local":"nofill_tcl":"RUN_do_streamout_nofill_tcl":"Mode nofill, tcl"
"do_pdv":"-drac -type -64 -local":"script_basic":"A":"-type drc -local":"drc":"RUN_do_pdv_drc":"Run DRC local"
"do_pdv"::"script_basic":"A":"-type lvs -64":"lvs":"RUN_do_pdv_lvs":"Run LVS 64"
"do_pdv"::"script_basic":"A":"-type arc":"arc":"RUN_do_pdv_arc":"Run arc"
"do_pdv"::"script_basic":"A":"-type latch":"latch":"RUN_do_pdv_latch":"Run latch"
"do_pdv"::"script_basic":"A":"-type pad":"pad":"RUN_do_pdv_pad":"Run pad"
"do_place":"-fe -type -def -mode -effort -template -include -tiecell -tcl -nobackup -local -ver -se -lef -overwrite MSV MMMC MSV+MMMC":"script_basic":"A":"-fe -type place -def $defFile -ver $verilogFile -effort lo -mode time -nobackup -overwrite -local":"place":"RUN_do_place_place":"Basic"
"do_place"::"tool_basic":"A":"-fe -type scan -def $defFile -ver $verilogFile -effort med -mode congestion -nobackup -overwrite -local":"scan":"RUN_do_place_scan":"Type scan, effort med"
"do_place"::"tool_basic":"A":"-fe -type both -def $defFile -ver $verilogFile -effort hi -mode congestion -tiecell -nobackup -overwrite -local":"both":"RUN_do_place_both":"Type both, effort hi, tiecell"
"do_place"::"tool_basic":"A":"-fe -type place -def $defFile -ver $verilogFile -effort lo -mode time -include $includeTcl -nobackup -overwrite -local":"include":"RUN_do_place_include":
"do_clktree":"-fe -nondefault -include -spec -fix_drv -reconvergent -deltree -macro -no_preroute -no_clkgating_check -nobackup -tcl -overwrite -no_exit -local -se -top -stage -dspf -ver -def  -non­defaul t - includ e -spec":"script_basic":"A":"-fe -spec -local":"tcl":"RUN_do_clktree_tcl":"Create clock spec only."
"do_clktree"::"tool_basic":"A":"-fe -nondefault -fix_drv -reconvergent -no_clkgating_check -overwrite -nobackup":"normal":"RUN_do_clktree_normal":
"do_clktree"::"tool_basic":"A":"-fe -nondefault -fix_drv -reconvergent -no_clkgating_check -def $defFile -ver $verilogFile -include $includeTcl-overwrite -nobackup -local":"deltree":"RUN_do_clktree_deltree":
"do_clktree"::"tool_basic":"A":"-fe -nondefault -fix_drv -reconvergent -no_clkgating_check -def $defFile -ver $verilogFile -macro $macroName -include $includeTcl-overwrite -nobackup":"macro":"RUN_do_clktree_macro":
"do_droute":"-fe -def -ver -type -mode -si -antenna -filler -celtic_eco -include -no_clkgating_check -clktree_report -tcl -overwrite -nobackup -no_exit -local -se -mem -diode -spec_ant_lef -max_xy -time -clk_route -def -ver -type -mode":"script_basic":"A":"-fe -def $defFile -ver $verilogFile -type full -mode time -si high -overwrite":"normal":"RUN_do_droute_normal":
"do_droute"::"tool_basic":"A":"-fe -def $defFile -ver $verilogFile -type full -mode time -si high -no_clkgating_check -overwrite":"noclkgating":"RUN_do_droute_noclkgating":
"do_droute"::"tool_basic":"A":"-fe -def $defFile -ver $verilogFile -type full -si high -no_clkgating_check -antenna diode -filler cap  -overwrite":"default-mode":"RUN_do_droute_default-mode":
"do_droute"::"tool_basic":"A":"-fe -def $defFile -ver $verilogFile -type celtic_eco  -si min -no_clkgating_check -antenna diode -filler normal  -overwrite":"si-min":"RUN_do_droute_si-min":
"do_droute"::"tool_basic":"A":"-fe -def $defFile -ver $verilogFile -type celtic_eco  -si min -no_clkgating_check -antenna diode -celtic_eco $ecoTcl -include $includeTcl  -overwrite":"include":"RUN_do_droute_include":
"do_extract":"-fe -timing -scale -type -tcl -overwrite -nobackup -se -design -dp -lef -def -local -tim­ing -scale":"script_basic":"A":"-fe -timing best -tcl":"best-tcl":"RUN_do_extract_best-tcl":
"do_extract"::"tool_basic":"A":"-fe -timing typ -overwrite -local -overwrite":"typ-studio":"RUN_do_extract_typ-studio":
"do_extract"::"tool_basic":"A":"-fe -timing worst -type fe -scale 1.5 -nobackup":"worst-fe":"RUN_do_extract_worst-fe":
"do_ipo":"-studio -def -ver -spef -stage -type -path -slack -effort -include -no_clkgating_check -glitch -fe -mode -filler -density -antenna -extract -no_exit -si -tcl -overwrite -nobackup -local -def -ver -spef -stage -type -path -slack -effort":"A_stu dio":"A":"-studio -def $defFile -ver $verilogFile -stage prects -type setup -path all -effort lo -no_clkgating_check":"studio-setup":"RUN_do_ipo_studio-setup":
"do_ipo"::"tool_basic":"A":"-studio -def $defFile -ver $verilogFile -stage postroute -type both -path in2reg -effort lo -no_clkgating_check -glitch":"studio-both":"RUN_do_ipo_studio-both":
"do_ipo"::"tool_basic":"A":"-fe -def $defFile -ver $verilogFile -stage postroute -type hold -path reg2out -effort lo -no_clkgating_check -filler cap -antenna diode -si -overwrite":"fe-hold":"RUN_do_ipo_fe-hold":
"do_ipo"::"tool_basic/ A_m mmc/ A_stu dio":"A/C":"-fe -def $defFile -ver $verilogFile -spef $spefFile -stage postcts -type mmmc -path reg2out -effort med -density 0.9 -no_clkgating_check -filler cap -antenna layer -si -overwrite":"density":"RUN_do_ipo_density":
"do_ipo"::"tool_basic":"A":"-fe -def $defFile -ver $verilogFile -spef $spefFile -stage postcts -type mmmc -path reg2reg -effort med -slack 1 -no_clkgating_check -filler cap -antenna diode -si -overwrite":"slack":"RUN_do_ipo_slack":

In this file there are 4 QA categories:
QAcategory:script_basic, tool_basic,advanced:adv_studio,adv_msv,adv_mmmc and others
The user has to input the QA category and it can be one of the above.If the user inputs QA  category script_basic then only those lines containing the category script_ basic should be read from the input file and printed to an output file.I need a perl program for this.

To get you starting:
1) Ask the user for the input: use <STDIN>.<<
2) use a regex in a if condition: something like if (Input=~ /.script_basic./) >>made a mistake in previous msg, need to compare the  input with lines in the file.<<
3) write the output to a file.
It would helpful if you can post your code/part of it.

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